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General information
Type CPU / Microprocessor
Frequency (MHz) 120 (rated 150)
Bus speed (MHz) 60
Clock multiplier 2
Package 296-pin Staggered Ceramic Pin Grid Array
1.952″ x 1.952″ (4.96 cm x 4.96 cm)
Introduction date 5-Feb-96
Price at introduction $451
Architecture / Microarchitecture
Data width 32 (64-bit data bus) bit
Floating Point Unit Integrated
Level 1 cache size 256 bytes primary code cache
16 KB four-way set associative unified code/data write-back cache
Physical memory (GB) 4
Pipeline Dual 7-stage integer
Low power features
* Suspend mode
* Stop clock mode
* System Management mode
Electrical/Thermal parameters
Min/Recommended/Max V core (V) 3.135 / 3.3 / 3.6
Minimum/Maximum operating temperature (°C) ? 0 – 70
Minimum/Typical/Maximum power dissipation (W) 0.28 (Suspend mode) / 16.8 / 20.1
Type CPU / Microprocessor
Frequency (MHz) 266
Bus speed (MHz) 33
Clock multiplier 8
Package 320-pin Ceramic Staggered Pin Grid Array
1.952″ x 1.952″ (4.96 cm x 4.96 cm)
Architecture / Microarchitecture
Manufacturing process 0.35 micron 4-layer metal CMOS process
Data width 32 bit
Floating Point Unit Integrated
Level 1 cache size 16 KB write-back 4-way set associative unified instruction and
data cache
Physical memory (GB) 1
Features MMX multimedia instructions
Low power features
APM support
CPU only suspend
Suspend modulation
Full 3V suspend
On-chip peripherals
PCI controller
Display controller and 2D Graphics accelerator
64-bit synchronous DRAM controller
Memory Management Unit
Internal Bus Interface Unit
Electrical/Thermal parameters
V core (V) 2.9 ± 0.15
V I/O or secondary (V) 3.3 ± 0.16
Minimum/Typical/Maximum power dissipation (W) 3.26 (Suspend mode) / 5.87 / 10.7
Notes
Interfaces with Cx5520 or Cx5530 companion chips
Core Frequency: 33 MHz
Board Frequency: 33 MHz
Data bus (ext.): 32 Bit
Address bus: 32 Bit
Transistors: 600,000
Voltage: 3.3 V
Introduced: 12/1992
Manufactured: week 40/1993
L1 Cache: 1 KB
Package Type: Ceramic QFP-100
General information
Type CPU / Microprocessor
Frequency (MHz) 150 (rated 200)
Package 296-pin Staggered Ceramic Pin Grid Array
1.952″ x 1.952″ (4.96 cm x 4.96 cm)
Architecture / Microarchitecture
Floating Point Unit Integrated
Level 1 cache size 256 bytes primary code cache
16 KB four-way set associative unified code/data write-back cache
Physical memory (GB) 4
Pipeline Dual 7-stage integer
Electrical/Thermal parameters
Min/Recommended/Max V core (V) 2.63 / 2.8 / 2.97
Min/Recommended/Max V I/O or secondary (V) 3.15 / 3.3 / 3.45
Minimum/Maximum operating temperature (°C) 0 – 70
Minimum/Typical/Maximum power dissipation (W) 0.31 (Suspend mode) / 14.28 / 17.13
